JPEG DIGITAL IMAGE COMPRESSION MODULE

This product was developed under CNES contract.

The ICM is flexible, compact, rad-tolerant, and has very low power consumption. It can be used for lossy compression of fixed Y or color pictures or slow scan video in space applications.

The ICM is based on two ASICS developed by MMS :

• The ASP17 which makes Discrete Cosine Transform (DCT) of the input signal.
• The ASP16 vhich ensures COmpression and FOrmatting (COFO). It performs raster to block reordering, quantization, zigzag scanning, Huffman coding, formatting, autotest and control.

Function Description

• Implements JPEG revision 5 algorithm (Basic sequential DCT system with non adaptive Huffman coding)
• Performs a simple, programmable, non JPEG formatting of compressed data with picture headers and Group Of Blocks (GOB) headers
• All algorithmic and formating parameters are programmable (in PROM or downloadable RAM)
• 4 algorithmic modes (sets of parameters) supported
• (e.g. : JEPG or user defined, Y or color)
• Fully autonomous and high coverage autotest capability
• Power down mode
• INPUT : raser-scanned, 8 bit, digital pictures with video controls (picture sync, line sync, pixel clock)
• OUTPUT : bytes of compressed, formatted data at smoothed rate
• CONTROL : reset, power down and autotest request controls. Access to internal registers : scale factor, algorithmic mode, autotest signature, number of blocks per GOB...
• Software Codec Package (on SUN 4 or PC)
• Compression : exact emulation of the ICM chip set including user definable parameters
• Decompression

Features

• Compression ratio : 3 to 20
• Pixels per line : up to 1024, upgradable to 8192
• Lines per picture : not limited
• Data rate : 4 MPEL/S AT 14 MHz clock rate
• Picture quality
  • JPEG : no visual degradation for compression ratio of about 10
  • With flat quantization matrix : lowest possible rms error of 1.2 at compression ratio about 3.5
• Active Power :
  • 520 mW/Mpel/s typical
  • 750 mW/Mpels/s max
• Power down : 10 mW typical
• Temp range : - 550C to + 1250C
• Quality grade : up to SCC 9000 level B
• Rad-tolerance : 40 krads range
• Full CMOS design : ASICs, RAM, FIFO (MHS), HCT
• Packaging : chip set (CERDIP, CQFP 132) or SMT module (on request)
• Chip count : 13
• Surface : 6000 mm2 (CERDIP, CQFP)

Matra Marconi Space France.
37, Avenue Louis Breguet
B.P. 1
78146 VELIZY-VILLACOUBLAY
Fax : (1) 34 88 49 89